In general, a semiconductor chip is mounted on a printed circuit board (PCB), which is an important component of a system configuration, and the semiconductor chip is supplied with a driving voltage that is appropriate for performing the logic and functions associated with its intended use. In order to perform such a logic and function, the semiconductor chip receives a signal applied from a component exterior to the semiconductor chip.
An input buffer is designed to buffer an external signal and input the buffered signal to inside the semiconductor chip. The simplest input buffer is the static input buffer. The static input buffer is implemented as an inverter type in which a PMOS transistor and an NMOS transistor are coupled in series between a power supply voltage terminal and a ground voltage terminal. The static input buffer has an advantage in that its configuration is very simple. However, the static input buffer has weak resistance to noise, and it is therefore ineffective for use in a semiconductor chip having a narrow swing width or requiring a high operating frequency.
Therefore, a differential amplifier type input buffer having a strong resistance to noise is used in a semiconductor chip having a narrow swing width or requiring a high operating frequency.
FIG. 1 is a circuit diagram of a conventional input buffer.
As illustrated in FIG. 1, the conventional input buffer includes an amplification unit 100 and a buffer unit 110. The amplification unit 100 is driven by an external voltage VEXT in response to an enable signal EN to differentially amplify an input signal IN and a reference voltage VREF and thereby generate an output signal OUT. The buffer unit 110 is driven by an internal voltage VINT to buffer the output signal OUT and output an inverted output signal OUTB. The amplification unit 100 is an interface circuit which directly receives the input signal applied from the exterior. The buffer unit 110 is an internal circuit which buffers the output signal OUT differentially amplified in the amplification unit 100. In order to improve the operational reliability and reduce current consumption, the buffer unit 110 is driven by the internal voltage VINT, which is maintained at a more stable level than that of the external voltage VEXT.
However, since the level of the output signal OUT outputted by the amplification unit 100 is dependent on the level of the input signal IN and the level of the reference voltage VREF, the input level range of the reference voltage VREF is limited. Furthermore, while the output signal OUT inputted to the buffer unit 110 is driven by the external voltage VEXT having a level ranging from 1.5 V to 2.0 V, the inverted output signal OUTB outputted from the buffer unit 110 is driven by the internal voltage VINT having a level ranging from 1.2 V to 1.4 V. Consequently, the duty cycle of the output signal OUT is different from the duty cycle of the inverted output signal OUTB.
Referring to FIG. 2, when the duty cycle of the output signal OUT is 50%, that is, the high level pulse width X1 is equal to the low level pulse width X2, the duty cycle of the inverted output signal OUTB is less than 50%. That is, the low level pulse width Y1 of the inverted output signal OUTB is larger than the high level pulse width Y2. This occurs because the inverted output signal OUTB is driven by the internal voltage VINT having a lower level than that of the external voltage VEXT.
Accordingly, even though the circuit can provide an output signal OUT having the duty cycle of 50%, the duty cycle of the inverted output signal OUTB driven by the internal voltage VINT is less than 50%, causing a duty cycle error. As the duty cycle error increases, the characteristics of the input buffer are degraded.